The present invention relates to an improved insulated-gate field effect transistor (IGFET) having an inverse-T gate electrode and to a method of producing the same.
When a FET is made highly integrated, electric fields adjacent to the drain increase and the so called hot-carrier effect becomes likely. To prevent this phenomenon, certain methods of easing the electric field adjacent to the drain are suggested. For example, a Lightly Doped Drain (LDD) structure and another structure having a gate made overlap the drain to restrict an electric field adjacent to thereto.
As is well known, a method of delimiting channel length in a self-alignment manner is performed by doping source and drain impurities through ion implantation, using a gate electrode as a mask. Such an insulated-gate FET, has a gate electrode housing with an inverse-T section that includes a thin electrode portion overlapping both source and drain and a thick electrode portion which functions as a mask for doping source and drain impurities.
It is conventional to produce the above inverse-T gate electrode or a FET having the electrode, see The Inverse-T gate LDD (ITLDD) Transistor of T. Huang et al., IEDM Tech. Dig. p. 742, (1986) and The Gate-drain Overlapped LDD (GOLD) Structure in R. Izawa et al., IEDM Tech. Dig. p. 38, (1987). These prior art processes will now be described.
FIGS. 1 to 6 are sectional views showing the structure of an ITLDD transistor adjacent to a gate. Referring to FIG. 1, a gate insulating layer 2 made of SiO.sub.2 is formed on the surface of, for example, a p-type silicon wafer 1, and then a polysilicon layer 3 and a SiO.sub.2 layer 4 are formed sequentially. A resist mask 5 to mask a region of the polysilicon layer 3 constituting a leg of an inverse-T gate electrode is formed on the SiO.sub.2 layer 4.
The SiO.sub.2 layer 4, exposed out of the resist mask 5, is then etched so as to show the polysilicon layer 3; the polysilicon layer 3 is then etched a predetermined distance from the surface thereof. This etching leaves only the thin polysilicon layer 3 in the region which is exposed outside of the resist mask 5 as shown in FIG. 2.
After removing the resist mask 5, as shown in FIG. 3, n-type impurities are doped by ion implantation into the surface of the silicon wafer 1. In this ion implantation, a portion 3A, which has the initial thickness of the polysilicon layer 3 and constitutes a leg of an inverse-T gate, and the SiO.sub.2 layer 4 prevent impurities form being doped into the silicon wafer 1 directly lying thereunder. On the other hand, impurities are doped into the silicon wafer 1 through a thinned polysilicon layer 3B in the periphery of the leg 3A of the inverse-T gate. As a result, an n.sup.- source 6 and an n.sup.- drain 7 are formed.
Subsequently, by depositing a thick SiO.sub.2 layer on the surface of the silicon wafer 1 and conducting well-known etch-backing on the SiO.sub.2 layer, a side wall 8 made of the above thick SiO.sub.2 is formed around the leg of the inverse-T gate as shown in FIG. 4. Then, the polysilicon layer 3, exposed outside of the SiO.sub.2 layer 4 and the side wall 8 is removed by etching, so that the inverse-T gate having a leg 3A and a top 3B both made of the polysilicon layer 3 is formed as shown in FIG. 5. The gate insulating layer 2 functions as an etch-stop for this etching.
Furthermore, n-type impurities are doped by ion implantation into the silicon wafer 1 by using the SiO.sub.2 layer 4, the polysilicon layer 3 thereunder and the side wall 8 as masks. Thereby, an n.sup.+ source 9 and an n.sup.+ drain 10 are formed as shown in FIG. 6 and an IGFET having the inverse-T gate is completed. This FET has a LDD structure in which the top of the inverse-T gate and the n.sup.- regions 6 and 7 overlap.
In the above inverse-T gate FET, since the thickness of the portion 3B which is formed by thinning the polysilicon layer 3, varies over the surface of the silicon wafer 1, the junction depth of the n.sup.- source 6 and the n.sup.- drain, formed by implanting ions passing through the thinned polysilicon layer 3B, is uneven, creating differences in the characteristics of transistors fabricated on the silicon wafer 1. The thickness non-uniformity of the polysilicon layer 3B causes another problem such that some areas on the surface of the silicon wafer 1 are etched during the process for removing the unmasked polysilicon layer 3B. This is because, in the areas, the thickness of the polysilicon layer 3B is smaller than the average thickness thereof throughout the silicon wafer 1 and the gate insulating layer 2 be subject to an excessive etching condition to fail to function as an etch-stop.
FIGS. 7 to 10 are sectional views showing an IGFET having the above GOLD structure adjacent to a gate. Referring to FIG. 7, a gate insulating layer 12 made of SiO.sub.2 is formed on the surface of a p-type silicon wafer 11. A first polysilicon layer 13 is deposited thereon and a natural oxide film 14 of 5 to 10 .ANG. in thickness is formed on the surface. Then, a second polysilicon layer 15 and a SiO.sub.2 layer are deposited in turn on the natural oxide film 14 and the SiO.sub.2 layer is patterned, thereby forming an insulating layer 16.
As shown in FIG. 8, the polysilicon layer 15 is etched by using the insulating layer 16 as a mask. This etching is performed on a condition that the natural oxide film 14 functions as an etch-stop. Then, a n.sup.- source 17 and n.sup.- drain 18 are formed by doping n-type impurities by ion implantation into the silicon wafer 11, while using the insulating layer 16 as a mask.
Subsequently, a thick SiO.sub.2 is deposited on the silicon wafer 11 and a well-known etch-backing is conducted on the SiO.sub.2 layer, thereby forming a side wall 19 made of the SiO.sub.2 on the sides of the polysilicon layer 15 and the insulating layer 16 as shown in FIG. 9. Then the polysilicon layer 13 exposed outside of the insulating layer 16 and the side wall 19 is removed by etching. Thus, an inverse-T gate having a leg composed of the polysilicon layer 15 and a top composed of the polysilicon layer 13 is formed.
N-type impurities are then doped by ion implantation into the silicon wafer 11 by using the insulating layer 16 and the side wall 19 as masks and an n.sup.+ source 20 and an n.sup.+ drain 21 are formed (FIG. 10) so that an IGFET having LDD structure, including an inverse-T gate electrode results.
In the above GOLD process, a thin insulating film such as a natural oxide film is used as an etch-stop for patterning the leg of the inverse-T gate. The insulating film disposed between these polysilicon layers 13 and 15 must be of a thickness capable of maintaining electrical conduction therebetween by the tunnel effect, the thickness being less than approximately 10 .ANG.. However, it is inevitable that overetching take place in order to pattern the polysilicon layer 15 due to the thickness distribution of the polysilicon layer 15 on the silicon wafer 11. As a result, when the natural oxide film 14 is etched, the polysilicon layer 13 is also etched in some areas. Therefore, the junction depth of the n.sup.- regions 17 and 18, which are formed by ion implantation through the polysilicon layer 13, is not uniform, creating differences in characteristics of the FET.
In the above process, an extremely high selective etching ratio is required for the natural oxide film 14 with respect to the polysilicon. Isotropic etching is typically employed to obtain a high selective etching ratio, accordingly, side etching of the polysilicon layer 15 occurs under the insulating layer 16 as shown in FIG. 8. As a result, the dimension of the inverse-T gate, especially, the size in the channel length direction is unlikely to be uniform in accordance with the thickness distribution of the polysilicon layer 15 on the silicon wafer 11, resulting in differences in the characteristics of the FET.
The present invention aims to solve the above problems of the prior art, such as ITLDD and GOLD. Therefore, a first object of the present invention is to provide a method of producing a IGFET having an inverse-T gate wherein the thickness of a top of the inverse-T gate is uniform. A second object of the present invention is to provide a method of producing a IGFET having an inverse-T gate, the method preventing the size of a leg of the inverse-T gate in the channel length direction from being uneven due to side etching in the leg. A third object of the present invention is is to uniformly produce a plurality of such IGFETs on a semiconductor substrate.